Meta details end-to-end co-design for production AI training on AMD GPUs

A combination of hardware-model co-design, analytical zero-warmup kernel selection, and agentic code translation yields up to 1.5x throughput gains for recommendation model training on AMD Instinct MI350X accelerators.

Primary source: arXiv:2610.22230: https://arxiv.org/abs/2610.22230

What’s new: Hyperscale AI infrastructure has long been constrained by deep vendor lock-in to NVIDIA hardware, driven by a decade of ecosystem optimization around CUDA and proprietary collective communication libraries. While alternative accelerators like AMD Instinct GPUs offer compelling raw compute and memory capacity, directly porting complex production workloads often results in severe performance regressions. In Architecting for Hardware Diversity: Meta’s End-to-End Co-Design for High-Performance AI Training on AMD GPUs (arXiv:2610.22230, 15 Oct 2026), Meta infrastructure researchers Haoyu Zhang, Arshad Rahman, Adnan Aziz, Ajith Prabhudev, and Amin Farmahini detail their methodology for deploying AMD Instinct MI350X accelerators alongside NVIDIA B200 GPUs for large-scale recommendation model training.

Rather than relying on naive one-to-one kernel translation, Meta formulated an end-to-end co-design strategy anchored by three principles. First, they restructured model architectures and memory allocations to exploit accelerator-specific strengths: utilizing the MI350X’s 288 GB HBM3e capacity (1.6x larger than the B200’s 192 GB) to store massive embedding tables and extended sequence contexts without expensive host offloading. Second, they developed Origami, an analytical performance modeling framework that predicts execution latencies across FP8 and BF16 GEMM configurations, achieving zero-warmup optimal kernel selection and bypassing days of empirical autotuning. Third, they built agentic LLM workflows that automatically analyze ROCm microarchitectural differences, generate custom memory-coalescing shims, and port CUDA kernels to Triton and HIP. Combined with RCCL collective communication tuning, GPU power excursion boosting, and rocSOLVER integration for the Shampoo second-order optimizer, the co-design pipeline achieved up to a 1.5x end-to-end training throughput improvement over direct porting baselines.

Why it matters: Diversifying data center compute away from single-vendor dependence is essential for supply-chain resilience, cost efficiency, and sustainable scaling. Meta’s production deployment demonstrates that alternative accelerators can compete effectively with frontier NVIDIA silicon when hardware characteristics dictate software structure rather than the reverse. Furthermore, by upstreaming the resulting optimizations, Triton kernels, and compiler passes directly to PyTorch and ROCm, Meta provides a reusable systems blueprint for the broader open-source AI infrastructure ecosystem.

Caveats: The reported benchmarks focus on large-scale deep learning recommendation models (DLRM architectures such as GDPA and HSTU), which feature distinct memory-bandwidth and sparse-embedding bottlenecks compared to dense frontier autoregressive transformer pretraining. While the analytical kernel selection model accurately handles structured matrix multiplications, irregular or dynamic sparse operations still demand manual profiling. Finally, closing the software maturity gap between CUDA and ROCm requires continuous engineering investment to maintain parity across rapid compiler and driver releases.